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19-2466; Rev 0; 4/02
Low-Power, 14-Bit Analog-to-Digital Converters with Parallel Interface
General Description
The MAX1065/MAX1066 14-bit, low-power successive approximation analog-to-digital converters (ADCs) feature automatic power-down, a factory-trimmed internal clock, and a high-speed, 14-bit-wide (MAX1065) or byte-wide (MAX1066) parallel interface. The devices operate from a single 4.75V to 5.25V analog supply and a 2.7V to 5.25V digital supply. The MAX1065/MAX1066 use an internal 4.096V reference or an external reference. The MAX1065/MAX1066 consume only 1.8mA at a sampling rate of 165ksps with external reference and 2.7mA with internal reference. AutoShutdownTM reduces supply current to 0.1mA at 10ksps. The MAX1065/MAX1066 are ideal for high-performance, battery-powered, data-acquisition applications. Excellent dynamic performance and low-power consumption in a small package make the MAX1065/ MAX1066 the best choice for circuits with demanding power consumption and space requirements. The 14-bit-wide MAX1065 is available in a 28-pin TSSOP package, and the byte-wide MAX1066 is available in a 20-pin TSSOP package. Both devices are available in either the 0C to +70C commercial, or the -40C to +85C extended temperature range.
Features
o 14-Bit-Wide (MAX1065) and Byte-Wide (MAX1066) Parallel Interface o High Speed: 165ksps Sample Rate o Accurate: 1LSB DNL (max), 1LSB INL (max) o 4.096V, 35ppm/C Internal Reference o External Reference Range 3.8V to 5.25V o Single 4.75V to 5.25V Analog Supply Voltage o 2.7V to 5.25V Digital Supply Voltage o Low Supply Current 1.8mA (External Reference) 2.7mA (Internal Reference) 0.1mA AutoShutdown Mode (10ksps, External Reference) o Small Footprint 28-Pin TSSOP Package (14-Bit Wide) 20-Pin TSSOP Package (Byte Wide)
MAX1065/MAX1066
Applications
Temperature Sensor/Monitor Industrial Process Control I/O Boards Data-Acquisition Systems Cable/Harness Tester Accelerometer Measurements Digital Signal Processing
PART MAX1065ACUI MAX1065BCUI MAX1065CCUI MAX1065AEUI MAX1065BEUI MAX1065CEUI MAX1066ACUP MAX1066BCUP
0.1F P DATA BUS
Ordering Information
TEMP RANGE 0C to 70C 0C to 70C 0C to 70C -40C to +85C -40C to +85C -40C to +85C 0C to 70C 0C to 70C 0C to 70C -40C to +85C -40C to +85C -40C to +85C PINPACKAGE 28 TSSOP 28 TSSOP 28 TSSOP 28 TSSOP 28 TSSOP 28 TSSOP 20 TSSOP 20 TSSOP 20 TSSOP 20 TSSOP 20 TSSOP 20 TSSOP INL 1 2 3 1 2 3 1 2 3 1 2 3
Typical Operating Circuit
5V ANALOG 0.1F 5V DIGITAL
MAX1066CCUP MAX1066AEUP MAX1066BEUP MAX1066CEUP
AVDD ANALOG INPUT AIN R/C CS RESET AGND
DVDD D0-D13
MAX1065
EOC REF REFADJ DGND 0.1F 1F
Pin Configurations appear at end of data sheet. AutoShutdown is a registered trademark of Maxim Integrated Products, Inc.
________________________________________________________________ Maxim Integrated Products
1
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Low-Power, 14-Bit Analog-to-Digital Converters with Parallel Interface MAX1065/MAX1066
ABSOLUTE MAXIMUM RATINGS
AVDD to AGND .........................................................-0.3V to +6V DVDD to DGND.........................................................-0.3V to +6V AGND to DGND.....................................................-0.3V to +0.3V AIN, REF, REFADJ to AGND....................-0.3V to (AVDD + 0.3V) CS, HBEN, R/C, RESET to DGND ............................-0.3V to +6V Digital Output (D13-D0, EOC) to DGND ..................................................-0.3V to (DVDD + 0.3V) Maximum Continuous Current Into Any Pin ........................50mA Continuous Power Dissipation (TA = +70C) 20-Pin TSSOP (derate 10.9mW/C above +70C) .......879mW 28-Pin TSSOP (derate 12.8mW/C above +70C) .....1026mW Operating Temperature Ranges MAX106_ _CU_ ...................................................0C to +70C MAX106_ _EU_ ................................................-40C to +85C Storage Temperature Range .............................-65C to +150C Junction Temperature ......................................................+150C Lead Temperature (soldering, 10s) .................................+300C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(AVDD = DVDD = 5V, external reference = 4.096V, CREF = 1F, CREFADJ = 0.1F, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.)
PARAMETER DC ACCURACY Resolution Relative Accuracy (Note 1) Differential Nonlinearity Transition Noise Offset Error Gain Error Offset Drift Gain Drift DYNAMIC PERFORMANCE (fIN(SINE-WAVE) = 1kHz, VIN = 4.096VP-P, 165ksps) Signal-to-Noise Plus Distortion Signal-to-Noise Ratio Total Harmonic Distortion Spurious-Free Dynamic Range Full-Power Bandwidth Full-Linear Bandwidth CONVERSION RATE Sample Rate Aperture Delay Aperture Jitter ANALOG INPUT Input Range Input Capacitance VAIN CAIN 0 40 VREF V pF fSAMPLE 40 100 165 ksps ns ps SINAD SNR THD SFDR -3dB point SINAD > 81dB 87 81 82 84 84 -99 102 4 20 -86 dB dB dB dB MHz kHz (Note 2) N MAX106_A INL DNL MAX106_B MAX106_C No missing codes over temperature RMS noise, includes quantization noise 0.32 0.2 0.002 0.6 0.2 1 0.02 14 1 2 3 1 LSB LSBRMS mV %FSR ppm/C ppm/C LSB Bits SYMBOL CONDITIONS MIN TYP MAX UNITS
2
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Low-Power, 14-Bit Analog-to-Digital Converters with Parallel Interface
ELECTRICAL CHARACTERISTICS (continued)
(AVDD = DVDD = 5V, external reference = 4.096V, CREF = 1F, CREFADJ = 0.1F, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.)
PARAMETER INTERNAL REFERENCE REF Output Voltage REF Output Tempco REF Short-Circuit Current Capacitive Bypass at REFADJ Capacitive Bypass at REF REFADJ Input Leakage Current EXTERNAL REFERENCE REFADJ Buffer Disable Threshold REF Input Voltage Range REF Input Current IREF To power-down the internal reference Internal reference disabled VREF = 4.096V, fSAMPLE = 165ksps Shutdown mode 0.7 x DVDD 0.3 x DVDD VIH = 0 or DVDD 0.1 0.1 15 ISOURCE = 0.5mA, DVDD = 2.7V to 5.25V, AVDD = 5.25V ISINK = 1.6mA, DVDD = 2.7V to 5.25V, AVDD = 5.25V D0-D13 0.1 15 DVDD 0.4 1 AVDD 0.4 3.8 62 0.1 AVDD 0.1 AVDD 120 V V A VREF TCREF IREFSC CREFADJ CREF IREFADJ 0.1 1 20 4.056 4.096 35 10 4.136 V ppm/C mA F F A SYMBOL CONDITIONS MIN TYP MAX UNITS
MAX1065/MAX1066
DIGITAL INPUTS/OUTPUTS (CS, R/C, EOC, D0-D13, RESET, HBEN) Input High Voltage Input Low Voltage Input Leakage Current Input Hysteresis Input Capacitance Output High Voltage VIH VIL IIN VHYST CIN VOH
V
A V pF V
Output Low Voltage Three-State Leakage Current Three-State Output Capacitance POWER REQUIREMENTS Analog Supply Voltage Digital Supply Voltage
VOL IOZ COZ
0.4 10
V A pF
AVDD DVDD 165ksps Internal reference 100ksps 10ksps 1ksps 165ksps External reference 100ksps 10ksps 1ksps
4.75 2.7 2.7 2.0 1.0 1.0 1.8 1.1 0.1 0.01
5.25 AVDD 3.2
V V
Analog Supply Current
IAVDD
2.3
mA
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Low-Power, 14-Bit Analog-to-Digital Converters with Parallel Interface MAX1065/MAX1066
ELECTRICAL CHARACTERISTICS (continued)
(AVDD = DVDD = 5V, external reference = 4.096V, CREF = 1F, CREFADJ = 0.1F, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.)
PARAMETER SYMBOL CONDITIONS 165ksps Digital Supply Current IDVDD D0-D13 = all zeros 100ksps 10ksps 1ksps Full power-down Shutdown Supply Current (Note 3) ISHDN REF and REF buffer enabled (standby mode) IAVDD IDVDD IAVDD IDVDD MIN TYP 0.5 0.3 0.03 0.003 0.05 0.5 1.0 0.5 68 5 5 1.2 5 mA A mA A dB MAX 0.7 mA UNITS
Power-Supply Rejection Ratio (Note 4)
PSRR
AVDD = 5V, 5%, full-scale input
TIMING CHARACTERISTICS (Figures 1 and 2)
(AVDD = 4.75V to 5.25V, DVDD = 2.7V to AVDD, external reference = 4.096V, CREF = 1F, CREFADJ = 0.1F, CD13-D0, CEOC = 20pF, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.)
PARAMETER Acquisition Time Conversion Time CS Pulse Width High CS Pulse Width Low R/C to CS Fall Setup Time R/C to CS Fall Hold Time CS to Output Data Valid HBEN Transition To Output Data Valid (MAX1066 only) EOC Fall To CS Fall CS Rise To EOC Rise Bus Relinquish Time (Note 5) SYMBOL tACQ tCONV tCSH tCSL tDS tDH tDO VDVDD = 4.75V to 5.25V VDVDD = 2.7V to 5.25V VDVDD = 4.75V to 5.25V VDVDD = 2.7V to 4.74V VDVDD = 4.75V to 5.25V tDO1 VDVDD = 2.7V to 4.74V tDV tEOC tBR VDVDD = 4.75V to 5.25V VDVDD = 2.7V to 4.74V VDVDD = 4.75V to 5.25V VDVDD = 2.7V to 4.74V 0 40 80 40 80 80 ns ns ns (Note 5) (Note 5) VDVDD = 4.75V to 5.25V VDVDD = 2.7V to 4.74V 40 40 60 0 40 60 40 80 40 ns CONDITIONS MIN 1.1 4.7 TYP MAX UNITS s ns ns ns ns ns
Note 1: Relative accuracy is the deviation of the analog value at any code from its theoretical value after offset and gain errors have been removed. Note 2: Offset nulled. Note 3: Maximum specification is limited by automated test equipment. Note 4: Defined as the change in positive full scale caused by a 5% variation in the nominal supply. Note 5: To ensure best performance, finish reading the data and wait tBR before starting a new acquisition.
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Low-Power, 14-Bit Analog-to-Digital Converters with Parallel Interface
Typical Operating Characteristics
(AVDD = DVDD = 5V, external reference = 4.096V, CREF = 1F, CREFADJ = 0.1F, TA = +25C, unless otherwise noted.)
IAVDD + IDVDD SUPPLY CURRENT vs. SAMPLE RATE
MAX1065/MAX1066 toc02 MAX1065/MAX1066 toc03
MAX1065/MAX1066
DNL vs. OUTPUT CODE
0.8 0.6 0.4 DNL (LSB) 0.2 0 -0.2 -0.4 -0.6 -0.8 -1.0 0 4096 8192 OUTPUT CODE 12288 16384
MAX1065/MAX1066 toc01
INL vs. OUTPUT CODE
2.0 1.5 1.0 INL (LSB) 0.5 0 -0.5 -1.0 -1.5 -2.0 0 4096 8192 OUTPUT CODE 12288 16384 0.0001 0.01 10
1.0
1 SUPPLY CURRENT (mA)
0.1
0.01
0.001
0.1
1
10
100
1000
CONVERSION RATE (ksps)
IAVDD + IDVDD SUPPLY CURRENT vs. TEMPERATURE
MAX1065/MAX1066 toc04
IAVDD + IDVDD SHUTDOWN CURRENT vs. TEMPERATURE
MAX1065/MAX1066 toc05
INTERNAL REFERENCE vs. TEMPERATURE
4.126 INTERNAL REFERENCE (V) 4.116 4.106 4.096 4.086 4.076 4.066 4.056
MAX1065/MAX1066 toc06
3.5 3.0 SUPPLY CURRENT (mA) 2.5 2.0 1.5 1.0 0.5 SAMPLE RATE = 165ksps 0 -40 -20 0 20 40 60 80 TEMPERATURE (C)
5.0 4.5 SHUTDOWN CURRENT (A) 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 -40 -20 0 20 40 60 80 TEMPERATURE (C)
4.136
-40
-20
0
20
40
60
80
TEMPERATURE (C)
OFFSET ERROR vs. TEMPERATURE
MAX1065/MAX1066 toc07
GAIN ERROR vs. TEMPERATURE
MAX1065/MAX1066 toc08
SINAD vs. FREQUENCY
90 80 70 SINAD (dB) 60 50 40 30 20 10 0 SAMPLE RATE = 165ksps 0.1 1 10 100
MAX1065/MAX1066 toc09
1000 800 600 OFFSET ERROR (V) 400 200 0 -200 -400 -600 -800 0 -40 -20 0 20 40 60 80 TEMPERATURE (C)
0.020 0.015 GAIN ERROR (%FSR) 0.010 0.005 0 -0.005 -0.010 -0.015 -0.020 -40 -20 0 20 40 60 80 TEMPERATURE (C)
100
FREQUENCY (kHz)
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Low-Power, 14-Bit Analog-to-Digital Converters with Parallel Interface MAX1065/MAX1066
Typical Operating Characteristics (continued)
(AVDD = DVDD = 5V, external reference = 4.096V, CREF = 1F, CREFADJ = 0.1F, TA = +25C, unless otherwise noted.)
TOTAL HARMONIC DISTORTION vs. FREQUENCY
MAX1065/MAX1066 toc10
SPURIOUS-FREE DYNAMIC RANGE vs. FREQUENCY
MAX1065/MAX1066 toc11
FFT AT 1kHz
SAMPLE RATE = 165ksps -20 MAGNITUDE (dB) -40 -60 -80 -100 -120
MAX1065/MAX1066 toc12
0 -10 -20 -30 THD (dB) -40 -50 -60 -70 -80 -90 -100 -110 0.1 1 10 SAMPLE RATE = 165ksps
110 100 90 80 SFDR (dB) 70 60 50 40 30 20 10 0 SAMPLE RATE = 165ksps 0.1 1.0 10
0
-140 0 20 40 FREQUENCY (kHz) 60 80
100
100
FREQUENCY (kHz)
FREQUENCY (kHz)
Pin Description
PIN MAX1065 1 2 3 4 5 6 7 8 MAX1066 1 2 3 4 -- -- -- -- D6 D7 D8 D9 D10 D11 D12 D13 NAME MAX1065 MAX1066 D4/D12 D5/D13 D6/0 D7/0 -- -- -- -- Three-State Digital Data Output Three-State Digital Data Output. D13 is the MSB. Three-State Digital Data Output Three-State Digital Data Output Three-State Digital Data Output Three-State Digital Data Output Three-State Digital Data Output Three-State Digital Data Output (MSB) Read/Convert Input. Power up and put the MAX1065/MAX1066 in acquisition mode by holding R/C low during the first falling edge of CS. During the second falling edge of CS the level on R/C determines whether the reference and reference buffer power down or remain on after conversion. Set R/C high during the second falling edge of CS to power down the reference and buffer, or set R/C low to leave the reference and buffer powered up. Set R/C high during the third falling edge of CS to put valid data on the bus. End Of Conversion. EOC drives low when conversion is complete. Analog Supply Input. Bypass with a 0.1F capacitor to AGND. Analog Ground. Primary analog ground (star ground). Analog Input Analog Ground. Connect Pin 14 to Pin 12 (MAX1065). Connect Pin 10 to Pin 8 (MAX1066). FUNCTION
9
5
R/C
10 11 12 13 14
6 7 8 9 10
EOC AVDD AGND AIN AGND
6
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Low-Power, 14-Bit Analog-to-Digital Converters with Parallel Interface
Pin Description (continued)
PIN MAX1065 15 MAX1066 11 NAME MAX1065 MAX1066 FUNCTION Reference Buffer Output. Bypass REFADJ with a 0.1F capacitor to AGND for internal reference mode. Connect REFADJ to AVDD to select external reference mode. Reference Input/Output. Bypass REF with a 1F capacitor to AGND for internal reference mode. External reference input when in external reference mode. Reset Input. Logic high resets the device. High Byte-Enable Input. Used to multiplex the 14-bit conversion result. 1: Most significant byte available on the data bus. 0: Least significant byte available on the data bus. Convert Start. The first falling edge of CS powers up the device and enables acquire mode when R/C is low. The second falling edge of CS starts conversion. The third falling edge of CS loads the result onto the bus when R/C is high. Digital Ground Digital Supply Voltage. Bypass with a 0.1F capacitor to DGND. D0/D8 D1/D9 D2/D10 D3/D11 -- -- -- -- No Connection. Do Not Connect (MAX1065). Three-State Digital Data Output (MAX1066). No Connection. Do Not Connect (MAX1065). Three-State Digital Data Output (MAX1066). Three-State Digital Data Output Three-State Digital Data Output Three-State Digital Data Output Three-State Digital Data Output Three-State Digital Data Output Three-State Digital Data Output
MAX1065/MAX1066
REFADJ
16 17 --
12 -- 13
REF RESET HBEN
18
14
CS
19 20 21 22 23 24 25 26 27 28
15 16 17 18 19 20 -- -- -- -- N.C. N.C. D0 D1 D2 D3 D4 D5
DGND DVDD
Functional Diagram
REFADJ 5k REFERENCE OUTPUT REGISTERS REF AIN CAPACITIVE DAC AGND RESET** CLOCK CS R/C *BYTE WIDE (MAX1066 ONLY) **16-BIT WIDE (MAX1065 ONLY) SUCCESSIVEAPPROXIMATION REGISTER AND CONTROL LOGIC 14 OR 8* 14 OR 8* D0-D13 OR D0/D8-D5/D13* HBEN* AVDD AGND DVDD DGND
MAX1065 MAX1066
EOC
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Low-Power, 14-Bit Analog-to-Digital Converters with Parallel Interface MAX1065/MAX1066
Detailed Description
Converter Operation
The MAX1065/MAX1066 use a successive-approximation (SAR) conversion technique with an inherent track-andhold (T/H) stage to convert an analog input into a 14-bit digital output. Parallel outputs provide a high-speed interface to most microprocessors (Ps). The Functional Diagram shows a simplified internal architecture of the MAX1065/MAX1066. Figure 3 shows a typical application circuit for the MAX1066.
DVDD 1mA
D0-D13 D0-D13
Analog Input
The equivalent input circuit is shown in Figure 4. A switched capacitor digital-to-analog converter (DAC) provides an inherent track-and-hold function. The single-ended input is connected between AIN and AGND.
Input Bandwidth
The ADC's input-tracking circuitry has a 4MHz smallsignal bandwidth, so it is possible to digitize highspeed transient events and measure periodic signals with bandwidths exceeding the ADC's sampling rate by using undersampling techniques. To avoid aliasing of unwanted high-frequency signals into the frequency band of interest, use antialias filtering. Internal protection diodes, which clamp the analog input to AVDD and/or AGND, allow the input to swing from AGND - 0.3V to AVDD + 0.3V, without damaging the device. If the analog input exceeds 300mV beyond the supplies, limit the input current to 10mA.
1mA DGND
CLOAD = 20pF
CLOAD = 20pF DGND b) HIGH-Z TO VOL, VOH TO VOL, AND VOL TO HIGH-Z
Track and Hold (T/H)
a) HIGH-Z TO VOH, VOL TO VOH, AND VOH TO HIGH-Z
Figure 1. Load Circuits for D0-D13 Enable Time, CS to D0-D13 Delay Time and Bus Relinquish Time
In track mode, the analog signal is acquired on the internal hold capacitor. In hold mode, the T/H switches open and the capacitive DAC samples the analog input.
tCSL CS
tCSH
tACQ R/C tDH EOC tCONV tDO DATA VALID tBR HI-Z REF POWERDOWN BIT tDS tDV tEOC
HI-Z D0-D13
HBEN* tDO1 D7/D13-D0/D8* HIGH/LOW BYTE VALID tBR HIGH/LOW BYTE VALID
*HBEN AND BYTE-WIDE DATA BUS AVAILABLE ON MAX1066 ONLY.
Figure 2. MAX1065/MAX1066 Timing Diagram 8 _______________________________________________________________________________________
Low-Power, 14-Bit Analog-to-Digital Converters with Parallel Interface
During the acquisition, the analog input (AIN) charges capacitor CDAC. The acquisition ends on the second falling edge of CS. At this instant, the T/H switches open. The retained charge on C DAC represents a sample of the input. In hold mode, the capacitive DAC adjusts during the remainder of the conversion time to restore node ZERO to zero within the limits of 14-bit resolution. At the end of the conversion, force CS low to put valid data on the bus. The time required for the T/H to acquire an input signal is a function of how quickly its input capacitance is charged. If the input signal's source impedance is high, the acquisition time lengthens and more time must be allowed between conversions. The acquisition time (tACQ) is the maximum time the device takes to acquire the signal. Use the following formula to calculate acquisition time: tACQ = 11(RS + RIN) x 35pF where R IN = 800, R S = the input signal's source impedance, and t ACQ is never less than 1.1s. A source impedance less than 1k does not significantly affect the ADC's performance. To improve the input-signal bandwidth under AC conditions, drive AIN with a wideband buffer (>4MHz) that can drive the ADC's input capacitance and settle quickly.
Internal Clock
The MAX1065/MAX1066 generate an internal conversion clock. This frees the microprocessor from the burden of running the SAR conversion clock. Total conversion time after entering hold mode (second falling edge of CS) to end-of-conversion (EOC) falling is 4.7s (max).
MAX1065/MAX1066
Applications Information
Starting a Conversion
CS and R/C control acquisition and conversion in the MAX1065/MAX1066 (Figure 2). The first falling edge of CS powers up the device and puts it into acquisition mode if R/C is low. The convert start is ignored if R/C is high. When powering up from shutdown, the MAX1065/ MAX1066 needs at least 10ms (CREFADJ = 0.1F, CREF = 1F) for the internal reference to wake up and settle before starting the conversion. The ADC may wake up from shutdown to an unknown state. Put the ADC in a known state by completing one "dummy" conversion. The MAX1065/ MAX1066 will be in a known state, ready for actual data acquisition, after the completion of the dummy conversion. A dummy conversion consists of one full conversion cycle. The MAX1065 provides an alternative reset function to reset the device (see RESET section).
Power-Down Modes
Select standby mode or shutdown mode with the R/C bit during the second falling edge of CS (see Selecting Standby or Shutdown Mode section). The MAX1065/ MAX1066 automatically enter either standby mode, reference and buffer on, or shutdown, reference and buffer off, after each conversion depending on the status of R/C during the second falling edge of CS.
5V ANALOG 5V DIGITAL
Selecting Standby or Shutdown Mode
The MAX1065/MAX1066 have a selectable standby or low-power shutdown mode. In standby mode, the ADC's internal reference and reference buffer do not power down between conversions, eliminating the need to wait for the reference to power up before performing the next conversion. Shutdown mode powers down the reference and reference buffer after completing a conversion. Supply current is greatly reduced when in shutdown mode. The reference and reference buffer require a minimum of 10ms (CREFADJ = 0.1F, CREF = 1F) to power up and settle from shutdown. The state of R/C at the second falling edge of CS selects which power-down mode the MAX1065/ MAX1066 enters upon conversion completion. Holding R/C low causes the MAX1065/MAX1066 to enter standby mode. The reference and buffer are left on after the conversion completes. R/C high causes the MAX1065/MAX1066 to enter shutdown mode and shut down the reference and buffer after conversion (Figures 5 and 6). When using an external reference, set the REF powerdown bit high for lowest current operation.
0.1F
0.1F P DATA BUS
AVDD ANALOG INPUT AIN R/C CS HIGH BYTE HBEN LOW BYTE AGND
DVDD D0-D7 OR D8-D13
MAX1066
EOC REF REFADJ DGND 0.1F 1F
Figure 3. Typical Application Circuit for MAX1066 _______________________________________________________________________________________ 9
Low-Power, 14-Bit Analog-to-Digital Converters with Parallel Interface MAX1065/MAX1066
Internal and External Reference
REF TRACK AIN CSWITCH 3pF HOLD AGND CDAC = 32pF CAPACITIVE DAC ZERO RIN 800 TRACK
HOLD
Internal Reference The internal reference of the MAX1065/MAX1066 is internally buffered to provide 4.096V (typ) output at REF. Bypass REF to AGND and REFADJ to AGND with 1F and 0.1F respectively. Fine adjustments can be made to the internal reference voltage by sinking or sourcing current at REFADJ. The input impedance at REFADJ is nominally 5k. The internal reference voltage is adjustable to 1.5% with the circuit of Figure 7.
AUTO-ZERO RAIL
Figure 4. Equivalent Input Circuit
Standby Mode
While in standby mode, the supply current is reduced to less than 1mA (typ). The next falling edge of CS with R/C low causes the MAX1065/MAX1066 to exit standby mode and begin acquisition. The reference and reference buffer remain active to allow quick turn-on time. Standby mode allows significant power savings while running at the maximum sample rate.
Shutdown Mode
In shutdown mode, the reference and reference buffer are shut down between conversions. Shutdown mode reduces supply current to 0.5A (typ) immediately after the conversion. The falling edge of CS with R/C low causes the reference and buffer to wake up and enter acquisition mode. To achieve 14-bit accuracy, allow 10ms (CREFADJ = 0.1F, CREF = 1F) for the internal reference to wake up. Increase wakeup time proportionally when using larger values of CREFADJ and CREF.
External Reference An external reference can be placed at either the input (REFADJ) or the output (REF) of the MAX1065/ MAX1066's internal buffer amplifier. When connecting an external reference to REFADJ, the input impedance is typically 5k. Using the buffered REFADJ input makes buffering the external reference unnecessary; however, the internal buffer output must be bypassed at REF with a 1F capacitor. Connect REFADJ to AVDD to disable the internal buffer. Directly drive REF using an external reference. During conversion, the external reference must be able to drive 100A of DC load current and have an output impedance of 10 or less. REFADJ's impedance is typically 5k. The DC input impedance of REF is 40k minimum. For optimal performance, buffer the reference through an op amp and bypass REF with a 1F capacitor. Consider the MAX1065/MAX1066's equivalent input noise (80VRMS) when choosing a reference.
ACQUISITION CS REF POWERDOWN BIT R/C
CONVERSION
DATA OUT CS R/C
ACQUISITION
CONVERSION
DATA OUT
REF POWERDOWN BIT
EOC
EOC
REF AND BUFFER
REF AND BUFFER
Figure 5. Selecting Standby Mode 10
Figure 6. Selecting Shutdown Mode
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Low-Power, 14-Bit Analog-to-Digital Converters with Parallel Interface MAX1065/MAX1066
OUTPUT CODE
5V 68k 100k
MAX1065 MAX1066
REFADJ
11...111 11...110 11...101
FULL-SCALE TRANSITION
150k
0.22F
1LSB = 00...011 00...010 00...001 00...000 0 1 2 3 FS FS - 3/2LSB INPUT VOLTAGE (LSB)
FS = VREF VREF 16384
Figure 7. MAX1065/MAX1066 Reference Adjust Circuit
Reading the Conversion Result
EOC is provided to flag the microprocessor when a conversion is complete. The falling edge of EOC signals that the data is valid and ready to be output to the bus. D0-D13 are the parallel outputs of the MAX1065/ MAX1066. These three-state outputs allow for direct connection to a microcontroller I/O bus. The outputs remain high-impedance during acquisition and conversion. Data is loaded onto the bus with the third falling edge of CS with R/C high after tDOns. Bringing CS high forces the output bus back to high-impedance. The MAX1065/MAX1066 then waits for the next falling edge of CS to start the next conversion cycle (Figure 2). The MAX1065 loads the conversion result onto a 14-bitwide data bus while the MAX1066 has a byte-wide output format. HBEN toggles the output between the most/least significant byte. The least significant byte is loaded onto the output bus when HBEN is low and the most significant byte is on the bus when HBEN is high (Figure 2).
Figure 8. MAX1065/MAX1066 Transfer Function
the required output voltage change before the beginning of the acquisition time. At the beginning of acquisition, the internal sampling capacitor array connects to AIN (the amplifier output) causing some output disturbance. Ensure that the sampled voltage has settled to within the required limits before the end of the acquisition time. If the frequency of interest is low, AIN can be bypassed with a large enough capacitor to charge the internal sampling capacitor with very little ripple. However, for AC use, AIN must be driven by a wideband buffer (at least 10MHz), which must be stable with the ADC's capacitive load (in parallel with any AIN bypass capacitor used) and also settle quickly. An example of this circuit using the MAX4434 is given in Figure 9.
RESET
Toggle RESET with CS high. The next falling edge of CS will begin acquisition. This reset is an alternative to the dummy conversion explained in the Starting a Conversion section.
Transfer Function
Figure 8 shows the MAX1065/MAX1066 output transfer function. The output is coded in standard binary.
ANALOG INPUT 10
MAX1065/ MAX1066
AIN 40pF
Input Buffer
Most applications require an input buffer amplifier to achieve 14-bit accuracy. If the input signal is multiplexed, the input channel should be switched immediately after acquisition, rather than near the end of or after a conversion. This allows more time for the input buffer amplifier to respond to a large step-change in input signal. The input amplifier must have a high enough slew rate to complete
MAX4434
Figure 9. MAX1065/MAX1066 Fast Settling Input Buffer 11
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Low-Power, 14-Bit Analog-to-Digital Converters with Parallel Interface MAX1065/MAX1066
Layout, Grounding, and Bypassing
For best performance, use printed circuit boards. Do not run analog and digital lines parallel to each other, and do not lay out digital signal paths underneath the ADC package. Use separate analog and digital ground planes with only one point connecting the two ground systems (analog and digital) as close to the device as possible. Route digital signals far away from sensitive analog and reference inputs. If digital lines must cross analog lines, do so at right angles to minimize coupling digital noise onto the analog lines. If the analog and digital sections share the same supply, then isolate the digital and analog supply by connecting them with a low-value (10) resistor or ferrite bead. The ADC is sensitive to high-frequency noise on the AVDD supply. Bypass AVDD to AGND with a 0.1F capacitor in parallel with a 1F to 10F low-ESR capacitor and the smallest capacitor closest to the device. Keep capacitor leads short to minimize stray inductance. In reality, there are other noise sources besides quantization noise: thermal noise, reference noise, clock jitter, etc. SNR is computed by taking the ratio of the RMS signal to the RMS noise, which includes all spectral components minus the fundamental, the first five harmonics, and the DC offset.
Signal-to-Noise Plus Distortion
Signal-to-noise plus distortion (SINAD) is the ratio of the fundamental input frequency's RMS amplitude to the RMS equivalent of all the other ADC output signals. SignalRMS SINAD(dB) = 20 x log (Noise + Distortion)RMS
Effective Number of Bits
Effective number of bits (ENOB) indicates the global accuracy of an ADC at a specific input frequency and sampling rate. An ideal ADC's error consists of quantization noise only. With an input range equal to the fullscale range of the ADC, calculate the effective number of bits as follows: ENOB = SINAD - 1.76 6.02
Definitions
Integral Nonlinearity
Integral nonlinearity (INL) is the deviation of the values on an actual transfer function from a straight line. This straight line can be either a best-straight-line fit or a line drawn between the end points of the transfer function, once offset and gain errors have been nullified. The static linearity parameters for the MAX1065/MAX1066 are measured using the end-point method.
Total Harmonic Distortion
Total harmonic distortion (THD) is the ratio of the RMS sum of the first five harmonics of the input signal to the fundamental itself. This is expressed as: 2 2 2 2 V2 + V3 + V4 + V5 THD = 20 x log V1 where V1 is the fundamental amplitude and V2 through V5 are the 2nd- through 5th-order harmonics.
Differential Nonlinearity
Differential nonlinearity (DNL) is the difference between an actual step width and the ideal value of 1LSB. A DNL error specification of 1LSB guarantees no missing codes and a monotonic transfer function.
Aperture Jitter and Delay
Aperture jitter is the sample-to-sample variation in the time between samples. Aperture delay is the time between the rising edge of the sampling clock and the instant when the actual sample is taken.
Spurious-Free Dynamic Range
Spurious-free dynamic range (SFDR) is the ratio of the RMS amplitude of the fundamental (maximum signal component) to the RMS value of the next largest frequency component.
Signal-to-Noise Ratio
For a waveform perfectly reconstructed from digital samples, signal-to-noise ratio (SNR) is the ratio of the full-scale analog input (RMS value) to the RMS quantization error (residual error). The ideal, theoretical minimum analog-to-digital noise is caused by quantization noise error only and results directly from the ADC's resolution (N-bits): SNR = (6.02 x N + 1.76)dB where N = 14 bits.
12
Chip Information
TRANSISTOR COUNT: 15,140 PROCESS: BiCMOS
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Low-Power, 14-Bit Analog-to-Digital Converters with Parallel Interface
Pin Configurations
TOP VIEW
MAX1065/MAX1066
D6 1 D7 2 D8 3 D9 4 D10 5 D11 6 D12 7 D13 8 R/C 9 EOC 10 AVDD 11 AGND 12 AIN 13 AGND 14
28 D5 27 D4 26 D3 25 D2 24 D1
D4/D12 1 D5/D13 2 D6/0 3 D7/0 4 R/C 5 EOC 6 AVDD 7 AGND 8 AIN 9 AGND 10
20 D3/D11 19 D2/D10 18 D1/D9 17 D0/D8
MAX1066
16 DVDD 15 DGND 14 CS 13 HBEN 12 REF 11 REFADJ
MAX1065
23 D0 22 N.C. 21 N.C. 20 DVDD 19 DGND 18 CS 17 RESET 16 REF 15 REFADJ
TSSOP
TSSOP
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Low-Power, 14-Bit Analog-to-Digital Converters with Parallel Interface MAX1065/MAX1066
Package Information
TSSOP,NO PADS.EPS
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
14 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 (c) 2002 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.

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